Quartus Prime Lite Edition —☐✕
Project Navigator ⚲☐✕
  • Compilation Hierarchy
Tasks ≡☐✕
Task
  • Compile Design
    • Analysis & Synthesis
      • Edit Settings
      • View Report
    • Fitter (Place & Route)
      • Edit Settings
    • Assembler (Generate programming files)
      • View Report
    • Timing Analysis
      • View Report
    • EDA Netlist Writer
  • Program Device (Open Programmer)
Home ✕ top.v ✕

Recent Projects

  • Project_Pong_Top.qpf (C:/Gits/new/Pong-Game-master/syn/Project_Pong_Top.qpf)
  • vending_machine.qpf (C:/Gits/new/vending_machine-master/vending_machine.qpf)
  • MLED.qpf (C:/Gits/new/MLED-master/MLED.qpf)
  • traffic.qpf (C:/Projects/traffic/traffic.qpf)
Compare EditionsBuy SoftwareDocumentationTrainingSupport
intel
IP Catalog⚲☐✕
Device Family
✕≡
  • Installed IP
    • Project Directory
      • No Selection Available
    • Library
      • Basic Functions
        • Arithmetic
        • Clocks; PLLs and Resets
        • On Chip Memory
      • DSP
        • Filters
        • Transforms
      • Interface Protocols
        • PCI Express
        • Ethernet
      • Memory Interfaces and Controllers
        • External Memory
      • Processors and Peripherals
        • Nios II Processor
      • University Program
        • Audio & Video
  • Search for Partner IP
Messages
TypeIDMessage
253020Default device 10M08DAF484C8G is automatically selected for the device family MAX 10
293000Quartus Prime Analysis & Synthesis was successful. 0 errors, 0 warnings
332140No Removal paths to report
TypeIDMessage
20030Parallel compilation is enabled and will use 4 of the 4 processors detected
System (3)Processing
Ready0%00:00:00
TRAFFIC - [C:/Users/user/FPGA/Xilinx/TRAFFIC/TRAFFIC.xpr] - Vivado 2017.2 —☐✕
Flow Navigator ⇅ ⇕ ? —
  • PROJECT MANAGER
    • Settings
    • Add Sources
    • Language Templates
    • IP Catalog
  • IP INTEGRATOR
    • Create Block Design
    • Open Block Design
    • Generate Block Design
  • SIMULATION
    • Run Simulation
  • RTL ANALYSIS
    • Open Elaborated Design
      • Report Methodology
      • Schematic
  • SYNTHESIS
    • Run Synthesis
    • Open Synthesized Design
      • Report Timing Summary
  • IMPLEMENTATION
    • Run Implementation
    • Open Implemented Design
      • Report Utilization
  • PROGRAM AND DEBUG
    • Generate Bitstream
    • Open Hardware Manager
      • Open Target
      • Program Device
PROJECT MANAGER - TRAFFIC ? ✕
Sources ? — ☐ ⧉ ✕
+0
  • Design Sources (1)
    • top (top.v)
  • Constraints
    • constrs_1
  • Simulation Sources
    • sim_1
HierarchyLibrariesCompile Order
Properties ? — ☐ ⧉ ✕
⇦⇨
Select an object to see properties
top.v C:/Users/user/FPGA/Xilinx/TRAFFIC/TRAFFIC.srcs/sources_1/new/top.v? — ☐ ⧉ ✕
Tcl ConsoleMessagesLogReportsDesign Runs ✕ ? — ☐ ⧉
start_gui
open_project C:/Users/user/FPGA/Xilinx/TRAFFIC/TRAFFIC.xpr
INFO: [Project 1-313] Project file moved from 'C:/Users/user/FPGA' since last save.
open_project: Time (s): cpu = 00:00:06 ; elapsed = 00:00:08 . Memory (MB): peak = 806.426
► Vivado Commands (2 infos)
► General Messages (1 info)
****** Vivado v2017.2 (64-bit)
**** SW Build 1909853 on Thu Jun 15 18:39:09 MDT 2017
**** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017
** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
No reports available.
+%
NameConstraintsStatusWNSTNSWHSTHSTPWSTotal PowerFailed RoutesLUTFFBRAMsURAM
⌄ ▷ synth_1constrs_1Not started
    ▷ impl_1constrs_1Not started
edt_zc702_workspace - hello_world/src/top.v - Vitis IDE —☐✕
■ Design◉ Debug
Debug ✕— ☐
  • Debugger_hello_world-Default (Local)
    • APU
      • ARM Cortex-A9 MPCore #0 (Breakpoint: main)
        • 0x0010053c main(): ../src/top.v, line 55
        • 0x00100d6c _start(): xil-crt0.S, line 77
      • ARM Cortex-A9 MPCore #1 (Running)
    • xc7z020
Explorer ✕Assistant— ☐
  • hello_world_system
    • hello_world
      • Debug
        • hello_world.elf
      • _ide
        • launch.json
      • src
        • top.v
        • helloworld.c
        • platform.c
        • platform.h
        • platform_config.h
        • lscript.ld
      • hello_world.prj
    • edt_zc702
      • platform.spr
helloworld.cplatform.ctop.v ✕xil_printf.h— ☐
VariablesBreakpointsRegisters ✕— ☐
NameHexDecimalDescription
r110x000000000
r120x000000000
sp0x0010a9c01092032
lr0x00100d701052016
pc0x0010053c1050940
cpsr0x6000015f1610612063
pc
Hex: 0x10053c, Decimal: 1050940, Octal: 04002474
MemoryDisassembly ✕— ☐
00100524: nop
main:
00100528: push {r11, lr}
0010052c: add r11, sp, #4
0010053c: bl +100 ; addr=0x001006a8
00100540: movw r0, #2616
00100544: movt r0, #16
00100548: bl +28 ; addr=0x0010065c
0010054c: movw r0, #2632
Console ✕Vitis Serial TerminalExecutablesVitis LogProblemsDebugger Console— ☐
Xilinx Software Command-Line Tool (XSCT) v2019.2
14:00:07 INFO : Launch script is exported to file 'C:\edt\edt_zc702_workspace\hello_world_system\_ide\scripts\debugger_hello_world-default.tcl'
14:00:07 INFO : Connected to target on host 'local' and port '3121'.
14:00:08 INFO : Processor reset is completed for 'ps7_cortexa9_0'.
14:00:09 INFO : Context for processor 'ps7_cortexa9_0' is selected.
-------------- End of Script --------------
Writable Smart Insert55 : 1 : 1204